www.siliconstandard.com 1 of 8 ssm 99 30 m 10 /21 /2004 rev. 1 .01 dual n- and dual p-channel enhancement-mode power mosfets simple drive requirement n-ch bv dss 30v low on-resistance r ds(on) 33mw full-bridge applications, such as i d 6.3a lcd monitor inverter p-ch bv dss -30v r ds(on) 55mw description i d -5.1a absolute maximum ratings symbol parameter rating units n-channel p-channel v ds drain-source voltage 30 -30 v v gs gate-source voltage 25 25 v i d @ t a =2 5 c continuous drain curren t 3 6.3 -5.1 a i d @ t a =7 0 c continuous drain curren t 3 4.2 -3.4 a i dm pulsed drain curren t 1 20 -20 a p d @ t a =2 5 c total power dissipation 2.0 w linear derating factor 0.016 w/ c t stg storage temperature range -55 to 150 c t j operating junction temperature range -55 to 150 c symbol value unit rthj-amb thermal resistance junction-ambient 3 max. 62.5 c /w parameter thermal data advanced power mosfets from silicon standard provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. n1g n1d/p1d n1s/n2s n2g p1g p1s/p2s n2d/p2d p2g so-8 n1g n1s p1g p1s p1n1d n2g n2s p2g p2s p2n2d the SSM9930M is in the so-8 package, which is widely preferred for commercial and industrial surface mount applications, and is well suited for applications such as low-voltage inverters and motor drives.
www.siliconstandard.com 2 of 8 ssm 99 30 m 10 /21 /2004 rev. 1 .01 n-channel electrical characteristics @ t j =25 o c (unless otherwise specified) symbol parameter test conditions min. typ. max. units bv dss drain-source breakdown voltage v gs =0v, i d =250ua 30 - - v d bv dss / d t j breakdown voltage temperature coefficient reference to 25c, i d =1ma - 0.037 -v/c r ds(on) static drain-source on-resistance 2 v gs =10v, i d =5a - - 33 mw v gs =4.5v, i d =3a - - 60 mw v gs(th) gate threshold voltage v ds =v gs , i d =250ua 1 - 3 v g fs forward transconductance v ds =10v, i d =5a - 5.2 - s i dss drain-source leakage current (t j =25 o c) v ds =30v, v gs =0v - - 1 ua drain-source leakage current (t j =70 o c) v ds =24v, v gs =0v - - 25 ua i gss gate-source leakage v gs =25v - - na q g total gate charge 2 i d =5a - 7.1 - nc q gs gate-source charge v ds =15v - 2.3 - nc q gd gate-drain ("miller") charge v gs =4.5v - 3.8 - nc t d(on) turn-on delay time 2 v ds =15v - 7.2 - ns t r rise time i d =1a - 10.4 - ns t d(off) turn-off delay time r g =6w ,v gs =10v - 18 - ns t f fall time r d =15w - 7.8 - ns c iss input capacitance v gs =0v - 600 - pf c oss output capacitance v ds =25v - 230 - pf c rss reverse transfer capacitance f=1.0mhz - 94 - pf source-drain diode symbol parameter test conditions min. typ. max. units v sd forward on voltage 2 i s =1.7a, v gs =0v - - 1.2 v t rr reverse recovery time i s =1.7a, v gs =0v - 21.4 - ns q rr reverse recovery charge di/dt=100a/s - 16 - nc 100
www.siliconstandard.com 3 of 8 ssm 99 30 m 10 /21 /2004 rev. 1 .01 p-channel electrical characteristics @ t j =25 o c (unless otherwise specified) symbol parameter test conditions min. typ. max. units bv dss drain-source breakdown voltage v gs =0v, i d =250ua -30 - - v d bv dss /d t j breakdown voltage temperature coefficient reference to 25c,i d =-1ma - -0.037 -v/c r ds(on) static drain-source on-resistance 2 v gs =-10v, i d =-5a - - 55 mw v gs =-4.5v, i d =-3a - - 100 mw v gs(th) gate threshold voltage v ds =v gs , i d =-250ua -1 - -3 v g fs forward transconductance v ds =-10v, i d =-5a - 4.8 - s i dss drain-source leakage current (t j =25 o c) v ds =-30v, v gs =0v - - -1 ua drain-source leakage current (t j = 70 o c) v ds =-24v, v gs =0v - - -25 ua i gss gate-source leakage v gs =- - na q g total gate charge 2 i d =-5a - 7.3 - nc q gs gate-source charge v ds =-15v - 2.5 - nc q gd gate-drain ("miller") charge v gs =-4.5v - 3.8 - nc t d(on) turn-on delay time 2 v ds =-15v - 10.8 - ns t r rise time i d =-1a - 7.6 - ns t d(off) turn-off delay time r g =6w ,v gs =-10v - 19.6 - ns t f fall time r d =15w - 17.5 - ns c iss input capacitance v gs =0v - 486 - pf c oss output capacitance v ds =-25v - 185.5 - pf c rss reverse transfer capacitance f=1.0mhz - 133.8 - pf source-drain diode symbol parameter test conditions min. typ. max. units v sd forward on voltage 2 i s =-1.7a, v gs =0v - - -1.2 v t rr reverse recovery time i s =-1.7a, v gs =0v - 21 - ns q rr reverse recovery charge di/dt=-100a/s - 15 - nc notes: 1.pulse width limited by max. junction temperature. 2.pulse width < 300us , duty cycle < 2%. 3.surface mounted on 1 in 2 copper pad of fr4 board ; 135c/w when mounted on min. copper pad. 25v 100
www.siliconstandard.com 4 of 8 ssm 99 30 m 10 /21 /2004 rev. 1 .01 n-channel fig 1. typical output characteristics fig 2. typical output characteristics fig 3. on-resistance vs. gate voltage fig 4. normalized on-resistance vs. junction temperature fig 5. forward characteristic of fig 6. gate threshold voltage vs. reverse diode junction temperature 0 5 10 15 20 25 0123456 v ds , drain-to-source voltage (v) i d , drain current (a) t a =25 o c 10v 4.0v 8.0v 6.0v v g =3.0v 0 5 10 15 20 25 0123456 v ds , drain-to-source voltage (v) i d , drain current (a) t a =150 o c 4.0v 6.0v 8.0v 10v v g =3.0v 20 25 30 35 40 45 34567891 0 11 v gs , gate-to-source voltage (v) r ds(on) (m w ) i d =5a t a =25c 0.6 0.8 1.0 1.2 1.4 1.6 1.8 -50 0 50 100 150 t j , junction temperature ( o c) normalized r ds(on) v g =10v i d =5a 1 1.2 1.4 1.6 1.8 2 -50 0 50 100 150 t j ,junction temperature ( o c) v gs(th) (v) 0.01 0.10 1.00 10.00 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 v sd , source-to-drain voltage (v) i s (a) t j =25 o c t j =150 o c
www.siliconstandard.com 5 of 8 ssm 99 30 m 10 /21 /2004 rev. 1 .01 n-channel fig 7. gate charge characteristics fig 8. typical capacitance characteristics fig 9. maximum safe operating area fig 10. effective transient thermal impedance fig 11. switching time waveform fig 12. gate charge waveform 0.01 0.1 1 10 100 0.1 1 10 100 v ds , drain-to-source voltage (v) i d (a) t a =25 o c single pulse 1ms 10ms 100ms 1s d c 0.001 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 10 100 1000 t , pulse width (s) normalized thermal response (r thja ) 0.01 0.05 0.1 0.2 duty=0.5 single pulse p dm t t duty factor = t/t peak t j = p dm x r thja + t a rthja = 135c/w 0.02 0 2 4 6 8 10 12 024681 01 21 4 q g , total gate charge (nc) v gs , gate to source voltage (v) i d =4.5a v ds =15v 10 100 1000 1 5 9 13 17 21 25 29 v ds , drain-to-source voltage (v) c (pf) f =1.0mhz ciss coss crss t d(on) t r t d(off) t f v ds v gs 10% 90% q v g 4.5v q gs q gd q g charge
www.siliconstandard.com 6 of 8 ssm 99 30 m 10 /21 /2004 rev. 1 .01 p-channel fig 1. typical output characteristics fig 2. typical output characteristics fig 3. on-resistance vs. gate voltage fig 4. normalized on-resistance vs. junction temperature fig 5. forward characteristic of fig 6. gate threshold voltage vs. reverse diode junction temperature 0.6 0.8 1 1.2 1.4 1.6 1.8 -50 0 50 100 150 t j , junction temperature ( o c) normalized r ds(on) v g = -10v i d =-5a 0 5 10 15 20 25 0123456 -v ds , drain-to-source voltage (v) -i d , drain current (a) t a =25 o c -10v -8.0v -6.0v -4.0v v g =-3.0v 0 5 10 15 20 25 0123456 -v ds , drain-to-source voltage (v) -i d , drain current (a) t a =150 o c -10v -4.0v -6.0v -8.0v v g =-3.0v 30 40 50 60 70 80 90 100 345678910 11 -v gs , gate-to-source voltage (v) r ds(on) (m w ) i d =-5a t a =2\5c 0.01 0.10 1.00 10.00 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 -v sd ,source-to-drain voltage (v) -i s (a) t j =25 o c t j =150 o c 1 1.5 2 2.5 3 -50 0 50 100 150 t j ,junction temperature ( o c) -v gs(th) (v)
www.siliconstandard.com 7 of 8 ssm 99 30 m 10 /21 /2004 rev. 1 .01 p-channel fig 7. gate charge characteristics fig 8. typical capacitance characteristics fig 9. maximum safe operating area fig 10. effective transient thermal impedance fig 11. switching time waveform fig 12. gate charge waveform 0.001 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 10 100 1000 t , pulse width (s) normalized thermal response (r thja ) 0.01 0.05 0.1 0.2 duty=0.5 single pulse p dm t t duty factor = t/t peak t j = p dm x r thja + t a rthja = 135c/w 0.02 0.01 0.1 1 10 100 0.1 1 10 100 -v ds , drain-to-source voltage (v) -i d (a) t a =25 o c single pulse 1s 1ms 10ms 100ms dc 10 100 1000 10000 1 5 9 13172 1 2529 -v ds , drain-to-source voltage (v) c (pf) f =1.0mhz ciss coss crss 0 2 4 6 8 10 12 14 024681 01 21 4 q g , total gate charge (nc) -v gs , gate to so ur ce voltage (v) i d =-5a v ds =-15v t d(on) t r t d(off) t f v ds v gs 10% 90% q v g 4.5v q gs q gd q g charge
in formation furnished by silicon standard corporation is believed to be accurate and reliable. however, silicon standard corporation makes no guarantee or warranty, expre ss or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. silicon standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. no license is granted, whether expressly or by im plication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of silicon standard corporation or any third parties. www.siliconstandard.com 8 of 8 ssm 99 30 m 10 /21 /2004 rev. 1 .01
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